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PIC18F46J11 FAMILY

DS39932D-page 66

2011 Microchip Technology Inc.

5.5

Configuration Mismatch (CM)

The Configuration Mismatch (CM) Reset is designed to

detect, and attempt to recover from, random memory

corrupting

events.

These

include

Electrostatic

Discharge (ESD) events, which can cause widespread

single bit changes throughout the device and result in

catastrophic failure.

In PIC18FXXJ Flash devices, the device Configuration

registers (located in the configuration memory space)

are continuously monitored during operation by com-

paring their values to complimentary shadow registers.

If a mismatch is detected between the two sets of

registers, a CM Reset automatically occurs. These

events are captured by the CM bit (RCON<5>). The

state of the bit is set to ‘0’ whenever a CM event occurs;

it does not change for any other Reset event.

A CM Reset behaves similarly to a MCLR, RESET

instruction, WDT time-out or Stack Event Resets. As

with all hard and power Reset events, the device

Configuration Words are reloaded from the Flash

Configuration Words in program memory as the device

restarts.

5.6

Power-up Timer (PWRT)

PIC18F46J11 family devices incorporate an on-chip

PWRT to help regulate the POR process. The PWRT is

always enabled. The main function is to ensure that the

device voltage is stable before code is executed.

The Power-up Timer (PWRT) of the PIC18F46J11 family

devices is a 5-bit counter which uses the INTRC source

as the clock input. This yields an approximate time

interval of 32 x 32

s = 1 ms. While the PWRT is

counting, the device is held in Reset.

The power-up time delay depends on the INTRC clock

and will vary from chip-to-chip due to temperature and

process variation. See DC parameter 33 (TPWRT) for

details.

5.6.1

TIME-OUT SEQUENCE

The PWRT time-out is invoked after the POR pulse has

cleared. The total time-out will vary based on the status

of the PWRT. Figure 5-2, Figure 5-3, Figure 5-4 and

Figure 5-5 all depict time-out sequences on power-up

with the PWRT.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the PWRT will expire. Bringing

MCLR high will begin execution immediately if a clock

source is available (Figure 5-4). This is useful for

testing purposes, or to synchronize more than one

PIC18FXXXX device operating in parallel.

FIGURE 5-2:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

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